As known, contacting of micro-integrated electronic devices requires contact pads to be formed on the front of a wafer integrating components forming the electronic devices and connected to external connection pins through bonding wires.
It is also known that the continuous reduction of the dimensions and the corresponding increase in the components, which can be integrated in one and the same chip, involves an increase in the number of pins and the corresponding contact pads required for the external connection of the chip.
Consequently, the space required for the interconnections becomes an increasingly large fraction of the chip area. To avoid this problem, the actual dimensions of the bonding pads and the space between them would have to reduce; there are, however, limiting factors (minimum dimensions of the bonding wire; mechanical alignment tolerances of the wires on the pads) which cause the minimum dimensions areas of the pads to be of some tens of microns. These dimensions are particularly large if compared to the minimum lithographic dimensions, of the order of tenths of a micron.
It is therefore desirable to be able to arrange the pads also in different areas of the device such as on the back; on the other hand this is not easy to achieve because of the need to isolate the connections from the conductive regions of the device; to produce reliable electrical connections between the front of the device, on which the electrical connection metal lines run, and the back, on which the pads would be arranged; and to use steps compatible with the conventional standard process steps.
The arrangement of the contact pads on the back of the chip is also desirable in cases, such as in inkjet print heads, wherein it is necessary to have an upper surface which is completely planar and free from regions which are even partially projecting (due to the bonding regions), for example to permit frequent cleaning of the upper surface.